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fn7523 rev 3.00 page 1 of 19 march 9, 2006 fn7523 rev 3.00 march 9, 2006 el7585a tft-lcd power supply datasheet the el7585a represents a multiple output regulators for use in all large panel, tft-lcd applic ations. it features a single boost converter with integrated 3.5a fet, two positive ldos for v on and v logic generation, and a single negative ldo for v off generation. the boost converter can be programmed to oper ate in either p-m ode or pi-mode for improved load regulation. the el7585a also integrates f ault protection for all four channels. once a fault is detect ed, the device is latched off until the input supply or en is cycled . this device also features an integrated start-up sequence for v boost, v off , then v on or for v off , v boost , and v on sequencing. the latter requires a single external transistor. the timing of the start-up sequence is set using an external capacitor. the v logic output is const antly enabled, bu t does shut down when a fault condition is detected. the el7585a is specified for operation over the -40c to +85c temperature range. features ? 3.5a current limit fet options ? 3v to 5v input ? up to 20v boost out ? 1% regulation on all outputs ?v off -v boost -v on or v boost -v off -v on sequence control -v logic is on from start-up for el7585a ? programmable sequence delay ? fully fault protected ? thermal shutdown ? internal soft-start ? 20 ld qfn packages ? pb-free plus anneal available (rohs compliant) applications ? lcd monitors (15+) ? lcd-tv (up to 40+) ? notebook displays (up to 16) ? industrial/medical lcd displays pinout el7585a (20 ld qfn) top view 1 2 3 4 15 14 13 12 6 7 8 9 20 19 18 17 cdly delb lx1 lx2 fbp drvl fbl sgnd pg vdd en sgnd cint vref pgnd pgnd thermal pad 5 drvp 10 drvn 11 fbn 16 fbb ordering information part number part marking package tape & reel pkg. dwg. # EL7585AILZ (note) 7585ail z 20 ld 4x4 qfn (pb-free) - mdp0046 EL7585AILZ-t7 (note) 7585ail z 20 ld 4x4 qfn (pb-free) 7 mdp0046 EL7585AILZ-t13 (note) 7585ail z 20 ld 4x4 qfn (pb-free) 13 mdp0046 note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 100% matte tin plate termination fini sh, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
el7585a fn7523 rev 3.00 page 2 of 19 march 9, 2006 absolute maximum ratings (t a = 25c) thermal information v drvp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36v v drvn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v v delb, v lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24v thermal resistance (typical, notes 1, 2) ? ja (c/w) ? jc (c/w) qfn package. . . . . . . . . . . . . . . . . . . . 39 2.5 v drvl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-4 0c to +85c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves maximum continuous junction temperature . . . . . . . . . . . . . . 125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v dd = 5v, v boost = 11v, i load = 200ma, v on = 15v, v off = -5v, v logic = 2.5v, over temperature from -40c to 85c, unless otherwise specified. parameter description condition min typ max unit supply v s supply voltage 35.5v i s quiescent current enabled, lx not switching 1.7 2.5 ma disabled 700 900 a clock f osc oscillator frequency 900 1000 1100 khz boost v boost boost output range 5.5 20 v v fbb boost feedback voltage t a = 25c 1.192 1.205 1.218 v 1.188 1.205 1.222 v v f_fbb fbb fault trip point 0.9 v v ref reference voltage t a = 25c 1.19 1.215 1.235 v 1.187 1.215 1.238 v c ref v ref capacitor 22 100 nf d max maximum duty cycle 85 % i lxmax switch current limit 3.5 a i leak switch leakage current v lx = 16v 10 a r ds(on) switch on-resistance 160 m ? eff boost efficiency see curves 92 % i(v fbb ) feedback input bias current pl mode, v fbb = 1.35v 50 500 na ? v boost / ? v in line regulation c int = 4.7nf, i out = 100ma, v in = 3v to 5.5v 0.05 %/v ? v boost / ? i boost load regulation - p mode c int pin strapped to v dd , 50ma < i load < 250ma 3% ? v boost / ? i boost load regulation - pi mode c int = 4.7nf, 50ma < i o < 250ma 0.1 % v cint_t cint pl mode select threshold 4.7 4.8 v
el7585a fn7523 rev 3.00 page 3 of 19 march 9, 2006 v on ldo v fbp fbp regulation voltage i drvp = 0.2ma, t a = 25c 1.176 1.2 1.224 v i drvp = 0.2ma 1.172 1.2 1.228 v v f_fbp fbp fault trip point v fbp falling 0.82 0.87 0.92 v i fbp fbp input bias current v fbp = 1.35v -250 250 na gmp fbp effective transconductance v drvp = 25v, i drvp = 0.2 to 2ma 50 ms ? v on / ? i(v on )v on load regulation i(v on ) = 0ma to 20ma -0.5 % i drvp drvp sink current max v fbp = 1.1v, v drvp = 25v 2 4 ma i l_drvp drvp leakage current v fbp = 1.5v, v drvp = 35v 0.1 5 a v off ldo v fbn fbn regulation voltage i drvn = 0.2ma, t a = 25c 0.173 0.203 0.233 v i drvn = 0.2ma 0.171 0.203 0.235 v v f_fbn fnn fault trip point v fbn rising 0.38 0.43 0.48 v i fbn fbn input bias current v fbn = 0.2v -250 250 na gmn fbn effective transconductance v drvn = -6v, i drvn = 0.2ma to 2ma 50 ms ? v off / ? i(v off ) v off load regulation i(v off ) = 0ma to 20ma -0.5 % i drvn drvn source current max v fbn = 0.3v, v drvn = -6v 2 4 ma i l_drvn drvn leakage current v fbn = 0v, v drvn = -20v 0.1 5 a v logic ldo v fbl fbl regulation voltage i drvl = 1ma, t a = 25c 1.176 1.2 1.224 v i drvl = 1ma 1.174 1.2 1.226 v v f_fbl fbl fault trip point v fbl falling 0.82 0.87 0.92 v i fbl fbl input bias current v fbl = 1.35v -500 500 na g ml fbl effective transconductance v drvl = 2.5v, i drvl = 1ma to 8ma 200 ms ? v logic / ? i(v logic ) v logic load regulation i(v logic ) = 100ma to 500ma 0.5 % i drvl drvl sink current max v fbl = 1.1v, v drvl = 2.5v 8 16 ma i l_drl i l_drvl v fbl = 1.5v, v drvl = 5.5v 0.1 5 a sequencing t on turn on delay c dly = 0.22f 30 ms t ss soft-start time c dly = 0.22f 2 ms t del1 delay between a vdd and v off c dly = 0.22f 10 ms t del2 delay between v on and v off c dly = 0.22f 17 ms t del3 delay between v off and delayed v boost c dly = 0.22f 10 ms i delb delb pull-down current v delb > 0.6v 50 a v delb < 0.6v 1.4 ma c del delay capacitor 10 220 nf fault detection t fault fault time out c dly = 0.22f 50 ms electrical specifications v dd = 5v, v boost = 11v, i load = 200ma, v on = 15v, v off = -5v, v logic = 2.5v, over temperature from -40c to 85c, unless otherwise specified. (continued) parameter description condition min typ max unit
el7585a fn7523 rev 3.00 page 4 of 19 march 9, 2006 ot over-temperature threshold 140 c i pg pg pull-down current vpg>0.6v 15 a vpg<0.6v 1.7 ma logic enable v hi logic high threshold 2.2 v v lo logic low threshold 0.8 v i low logic low bias current 0.2 1 a i high logic high bias current at v en = 5v 12 18 24 a electrical specifications v dd = 5v, v boost = 11v, i load = 200ma, v on = 15v, v off = -5v, v logic = 2.5v, over temperature from -40c to 85c, unless otherwise specified. (continued) parameter description condition min typ max unit pin descriptions pin name pin number description 1 cdly a capacitor connected from this pin to gnd sets the delay time for start-up sequence and sets the fault timeout time 2 delb open drain output for gate drive of optional v boost delay fet 3, 4 lx1, lx2 drain of the internal n channel boost fet; for el75 86, pin 4 is not connected 5 drvp positive ldo base drive; open drain of an internal n chann el fet 6 fbp positive ldo voltage feedbac k input pin; regulates to 1.2v nominal 7 drvl logic ldo base drive; open drain of an internal n channel fet 8 fbl logic ldo voltage feedback input pin; regulates to 1.2v nom inal 9, 17 sgnd low noise signal ground 10 drvn negative ldo base drive; open drain of an internal p chan nel fet 11 fbn negative ldo voltage feedback input pin; regulates to 0.2v nominal 12, 13 pgnd power ground, connected to source of internal n chann el boost fet 14 vref bandgap voltage bypass, connect a 0.1f to sgnd 15 cint v boost integrator output, connect capacit or to sgnd for pi mode or con nect to v dd for p mode operation 16 fbb boost regulator voltage feedback input pin; regulates to 1 .2v nominal 18 en enable pin, high=enable; low or floating=disable 19 vdd positive supply 20 pg push-pull gate drive of opt ional fault protection fet, whe n chip is disabled or when a fault has been detected, this is high
el7585a fn7523 rev 3.00 page 5 of 19 march 9, 2006 typical performance curves figure 1. v boost efficiency at v in =3v (pi mode) figure 2. v boost efficiency at v in =5v (pi mode) figure 3. v boost efficiency at v in =3v (p mode) figure 4. v boost efficiency at v in =5v (p mode) figure 5. v boost load regulation at v in =3v (pi mode) figure 6. v boost load regulation at v in =5v (pi mode) 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 i out (a) efficiency (%) v o =9v v o =12v v o =15v 0 10 20 30 40 50 60 70 80 90 100 00.511.5 i out (a) efficiency (%) v o =9v v o =12v v o =15v 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.7 i out (a) efficiency (%) 0.1 0.3 0.5 v o =9v v o =12v v o =15v 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 i out (a) efficiency (%) v o =9v v o =12v v o =15v -0.5 -0.4 -0.3 -0.2 -0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 i out (a) load regulation (%) v o =12v v o =9v v o =15v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 i out (a) load regulation (%) v o =9v v o =15v -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 v o =12v
el7585a fn7523 rev 3.00 page 6 of 19 march 9, 2006 figure 7. v boost load regulation at v in =3v (p mode) figure 8. v boost load regulation at v in =5v (p mode) figure 9. v on load regulation figure 10. v off load regulation figure 11. v logic load regulation figure 12. start-up sequence typical performance curves (continued) -8 -7 -6 -5 -4 -3 -2 -1 0 0 0.2 0.4 0.6 0.8 i out (a) load regulation (%) v o =9v v o =12v v o =15v -10 -8 -6 -4 -2 0 00.511.5 i out (a) load regulation (%) v o =9v v o =12v v o =15v load regulation (%) i out (ma) 0 -0.1 -0.3 -0.5 -0.6 0 20406080 -0.4 -0.2 load regulation (%) i out (ma) 0 -0.2 -0.8 -1.2 -1.4 020 6080100 -1 -0.6 40 -0.4 load regulation (%) i out (ma) 0 -0.2 -0.6 -1 -1.2 0 100 200 500 700 -0.8 -0.4 400 300 600 v cdly v logic v in en time (10ms/div) c dly =220nf
el7585a fn7523 rev 3.00 page 7 of 19 march 9, 2006 figure 13. start-up sequence figure 14. start-up sequence figure 15. start-up sequence figure 16. lx waveform - discontinuou s mode figure 17. lx waveform - continuous mode typical performance curves (continued) v cdly v logic v in v ref time (10ms/div) c dly =220nf time (10ms/div) avdd v logic v off v on c dly =220nf time (10ms/div) avdd v logic v off v on c dly =220nf v in =5v v out =13v i out =30ma time (400ns/div) v in =5v v out =13v i out =200ma time (400ns/div)
el7585a fn7523 rev 3.00 page 8 of 19 march 9, 2006 applications information the el7585a is a highly integr ated multiple output power solution for tft-lcd applications. the system consists of one high efficiency boost converter and three linear- regulator controllers (v on , v off , and v logic ) with multiple protection functions. a block di agram is shown in figure 18. table 1 lists the recommended components. the el7585a integr ates an n-channel mosfet boost converter to minimize exter nal component count and cost. the a vdd , v on , v off , and v logic output voltages are independently set using external resistors. v on , v off voltages require external c harge pumps wh ich are post regulated using the int egrated ldo controllers. ? pwm logic controller buffer oscillator slope compensation osc reference generator v ref gm amplifier uvlo comparator voltage amplifier current amplifier thermal shutdown ss + - uvlo comparator buffer uvlo comparator uvlo comparator ss + - en + - buffer shutdown & start-up control buffer fbp drvl fbl drvp fbb c int drvn fbn 0.4v 0.2v v ref v ref comp current limit comparator current ref pgnd lx figure 18. block diagram sgnd v dd pg cdly delb en table 1. recommended components designation description c 1 , c 2 , c 3 10f, 16v x5r cerami c capacito r (1206) tdk c3216x5r0j106k c 20 , c 31 4.7f, 25v x5r ceramic capacitor (1206) tdk c3216x5r1a475k d 1 1a 20v low leakage scho ttky rectifier (case 457- 04) on semi mbrm120et3 d 11 , d 12 , d 21 200ma 30v schottky barrier diode (sot-23) fairchild bat54s l 1 6.8h 1.3a inductor tdk slf6025t-6r8m1r3-pf q 1 -2.4 -20v p-channel 1.8v specified powertrench mosfet (supersot-3) fairchild fdn304p q 4 -2a -30v single p-channel logic level powertrench mosfet (supersot-3) fairchild fdn360p q 3 200ma 40v pnp amplifier (sot-23) fairchild mmbt3906 q 2 200ma 40v npn amplifier (sot-23) fairchild mmbt3904 q 5 1a 30v pnp low saturation amplifier (sot-23) fairchild fmmt549 table 1. recommended components (continued) designation description
el7585a fn7523 rev 3.00 page 9 of 19 march 9, 2006 boost converter the main boost converter is a c urrent mode pwm converter at a fixed frequency of 1mhz which enables the use of low profile inductors and multilaye r ceramic capacitors. this results in a compact, low cost power syst em for lcd panel design. the el7585a is designed for continuous current mode, but they can also operate in disco ntinuous current mode at light load. in continuous current mode, current flows continuously in the inductor during the en tire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by: where d is the duty cycle o f the switching mosfet. figure 19 shows the block diag ram of the boost regulator. it uses a summing amplifier arch itecture consisting of gm stages for voltage feedback, c urrent feedback and slope compensation. a comparator looks at the peak inductor current cycle by cycle and term inates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resisto r network should be li mited to maintain the overall converte r efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise bei ng coupled into the feedback pin. a resistor network in the order of 60k ? is recommended. the boost converter output vo ltage is determined by the following equation: the current through the mosf et is limited to 3.5a peak. this restricts the maximum o utput current based on the following equation: where ? il is peak to peak inductor ri pple current, and is set by: where f s is the switching frequency. a vdd v in --------------- - 1 1d C ------------- = + r 1 -------------------- - v ref ? = ? i l 2 -------- C ?? ?? v in v o --------- ? = ? i l v in l --------- d f s ---- - ? = iref iref fbb ifb ifb cint voltage amplifier lx pgnd shutdown & start-up control gm amplifier slope compensation buffer pwm logic current amplifier clock reference generator figure 19. block diagram of the boost regulator
el7585a fn7523 rev 3.00 page 10 of 19 march 9, 2006 the following table gives typical values (margins are considered 10%, 3%, 20%, 10%, and 15% on v in , v o , l, f s , and i omax : input capacitor an input capacitor is used to supply the peak charging current to the converter. it is recommended that c in be larger than 10f. the reflected ripple voltage will be smaller with larger c in . the voltage rating of input capacitor should be larger than maximum input voltage. boost inductor the boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. values of 3.3h to 10h are to match the internal slope compensation. the inductor must be able to handle the following average and peak current: rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the rectifier diode must meet the outpu t current and peak inductor current requirements. output capacitor the output capacitor supplies t he load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging an d discharging of the output capacitor. for low esr ceramic capaci tors, the output ripple is dominated by the charging and d ischarging of the output capacitor. the voltage rating o f the output capacitor should be greater than the ma ximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases . c out in the equation above assumes the effective value of the capacitor at a particular vo ltage and not the manufacturers st ated value, measured at zero volts. compensation the el7585a can opera te in either p m ode or pi mode. connecting the c int pin directly to v in will enable p mode; for better load regulation, use pi mode with a 4.7nf capacitor in series with a 10k resistor between c int and ground. this value may be r educed to improve transient performance, however, very l ow values will reduce loop stability. boost feedback resistors as the boost output voltage, a vdd , is reduced below 12v the effective voltage feedback in t he ic increases the ratio of voltage to current feedba ck at the summing comparator because r 2 decreases relative to r 1 . to maintain stable operation over the complete c urrent range of the ic, the voltage feedback to the f bb pin should be reduced proportionally, as a vdd is reduced, by means of a series resistor-capacit or network (r 7 and c 7 ) in parallel with r 1 , with a pole frequency (f p ) set to approximately 10khz for c 2 effective = 10f and 4khz for c 2 (effective) = 30f. r 7 = ((1/0.1 x r 2 ) - 1/r 1 )^-1 c 7 = 1/(2 x 3.142 x f p x r 7 ) pi mode c int (c 23 ) and r int (r 10 ) the ic is designed to operate with a minimum c 23 capacitor of 4.7nf and a minimum c 2 (effective) = 10f. note that, for high voltage a vdd , the voltage coefficient of ceramic capacitors (c 2 ) reduces their effe ctive capacitance greatly; a 16v 10f ceramic can drop to around 3f at 15v. to improve the transient load response of a vdd in pi mode, a resistor may be added in series with the c 23 capacitor. the larger the resistor the lower the overshoot but at the expense of stability of the converter loop - especially at high current s. with l = 10h, a vdd = 15v, c 23 = 4.7nf, c 2 (effective) should have a capacitance of greater than 10f. r int (r 7 ) can have values up to 5k ? for c 2 (effective) up to 20f and up to 10k for c 2 (effective) up to 30f. larger values of r int (r 7 ) may be possible if maximum a vdd load currents less than the current limit are used. to ensure a vdd stability, the ic shoul d be operated at the maximum desired current and then the transient load response of a vdd should be used to determine the maximum value of r int . table 2. v in (v) v o (v) l ( h) f s (mhz) i omax 3.3 9 6.8 1 1.040686 3.3 12 6.8 1 0.719853 3.3 15 6.8 1 0.527353 5 9 6.8 1 1.576797 5 12 6.8 1 1.090686 5 15 6.8 1 0.79902 i lavg i o 1d C ------------- = ? i l 2 -------- + = C v o ----------------------- - i o c out --------------- - 1 f s ---- - ? ? + ? =
el7585a fn7523 rev 3.00 page 11 of 19 march 9, 2006 operation of the delb output function an open drain delb output is provided to allow the boost output voltage, developed at c 2 (see application diagram), to be delayed via an external swi tch (q4) to a time after the v boost supply and negative v off charge pump supply have achieved regulation dur ing the star t-up sequence shown in figure 28. this then allows the a vdd and v on supplies to start-up from 0v instead of the normal offset voltage of v in -v diode (d 1 ) if q4 were n ot present. when delb is activated by the start-up sequencer, it sinks 50a allowing a controlled turn -on of q4 and charge-up of c 9 . c 16 can be used to control the turn-on time of q4 to reduce inrush current into c 9 . the potential divider formed by r 9 and r 8 can be used to limit the v gs voltage of q4 if required by the voltage rating of this device. when the voltage at delb falls to less than 0.6v, the sink current is increased to ~1.2ma to firmly pull delb to 0v. the voltage at delb is monitor ed by the fault protection circuit so that if the initial 50a sink current fails to pull delb below ~0.6v after the start-up sequencing has completed, then a fault condition will be det ected and a fault time-out ramp will be initiated on the c del capacitor (c 7 ). operation of the pg output function the pg output consis ts of an internal p ull-up pmos device to v in , to turn-off the external q1 protection switch and a current limited pull-down nmo s device which sinks ~15a allowing a controlled turn-o n of q1 gate ca pacitance. c o is used to control how fast q1 turns-on - limiting inrush current into c 1 . when the voltage at the pg pin falls to less than 0.6v, the pg sink current is i ncreased to ~1.2ma to firmly pull the pin to 0v. the voltage at pg is monitored by the fault protection circuit so that if the initial 15a sin k current fails to pull pg below ~0.6v after the start-up sequencing has completed, then a fault condition will be detected and a fault time-out ramp will be initiated on the c del capacitor (c 7 ). cascaded mosfet application a 20v n-channel mosfet is integrated in the boost regulator. for the applications where the output voltage is greater than 20v, an external cascaded mosfet is needed as shown in figure 20. the volt age rating of t he external mosfet should be greater than v boost . linear-regulator controllers (v on , v logic , and v off ) the el7585a includes three independent linear-regulator controllers, in which two ar e positive outp ut voltage (v on and v logic ), and one is negative. the v on , v off , and v logic linear-regulator controll er functional diagrams, applications circuits are show n in figures 21, 22, and 23 respectively. calculation of the linear regulator base-emitter resistors (r bl , r bp and r bn ) for the pass transistor of the linear regulator, low frequency gain (hfe) and unity gain freq. (f t ) are usually specified in the datasheet. the pass transistor adds a pole to the loop transfer function at f p =f t /hfe. therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. further improvement can be obtained by adding a base-emitter resistor r be (r bp , r bl , r bn in the functional block diagram), which incr ease the pole frequency to: f p =f t *(1+ hfe *re/r be )/hfe, where re=kt/qic. so choose the lowest value r be in the design as long as there is still enough base current (i b ) to support the maximum output current (i c ). we will take as an example the v logic linear regulator. if a fairchild fmmt549 pnp transis tor is used as the external pass transistor, q5 in the appl ication diagram, then for a maximum v logic operating requirement of 500ma the data sheet indicates hfe_min = 100. the base-emitter saturation v oltage is: vbe_max = 1.25v (note this is normally a vbe ~ 0.7v, however, for the q5 transistor an internal darlin gton arrangement is used to increase it's current gain, givi ng a 'base-emitter' voltage of 2xv be ). (note that using a high current darlington pnp transistor for q5 requires that v in > v logic + 2v. should a lower input voltage be required, then an ordinary high gain pnp transistor should be selected f or q5 so as to allow a lower collector-emitter saturation voltage). el7585a fb lx v boost v in figure 20. cascaded mosfet topology for high output voltage applications
el7585a fn7523 rev 3.00 page 12 of 19 march 9, 2006 for the el7585a, the minimum drive current is: i_drvl_min = 8ma the minimum base-emitter resistor, r bl , can now be calculated as: r bl _min = v be _max/(i_drvl_min - ic/hfe_min) = 1.25v/(8ma - 500ma/100) = 417 ? this is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; say 500 ? . larger values may be u sed to reduce quiescent current, however, regulation may be adversely affected, by supply noise if r bl is made too high in value. the v on power supply is used to p ower the positive supply of the row driver in the lcd panel. the dc-dc consists of an external diode-capacitor c harge pump powered from the inductor (lx) of the boost con verter, followed by a low dropout linear regulator (ldo_ on). the ldo_on regulator uses an external pnp transisto r as the pass element. the onboard ldo controller i s a wide band (>10mhz) transconductance amplifier ca pable of 4ma drive current, which is sufficient for up to 40ma or more output current under the low dropout condition (forced beta of 10). typical v on voltage supported by el75 85a ranges from +15v to +36v. a fault comparator is als o included for monitoring the output voltage. the under-volt age threshold is set at 25% below the 1.2v reference. the v off power supply is used to power the negative supply of the row driver i n the lcd panel. the dc-dc consists of an external diode-capacitor charge pump powered from the inductor (l x) of the boost converter, followed by a low dropout lin ear regulator (ldo_off). the ldo_off regulator uses an external npn transistor as the pass element. the onboard ld o controller is a wide band (>10mhz) transconductance amp lifier capable of 4ma drive current, which is sufficient fo r up to 40ma o r more output current under the low dropout c ondition (forced beta of 10). typical v off voltage supported by el7585a ranges from -5v to -20v. a fault comparator is also included for monitoring the output voltage. the undervoltage threshold is set at 200mv above the 0.2v reference level. the v logic power supply is used to power the logic circuitry within the lcd panel. the dc- dc may be powered directly from the low voltage input, 3 .3v or 5.0v, or it may be powered through the faul t protection switch. the ldo_logic regulator uses an external pnp transistor as the pass element. the onboar d ldo controller is a wide band (>10mhz) transconductanc e amplifier capable of 16ma drive current, w hich is sufficient fo r up to 160ma or - + - + 36v esd clamp gmp ldo_on pg_ldop 1: np fbp drvp 7k ? r bp v boost 0.1f 0.1f cp (to 36v) 20k ? r p2 r p1 c on v on (to 35v) lx 0.9v q3 figure 21. v on functional block diagram - + - + 36v esd clamp gmn ldo_off 1: nn fbn drvn 0.1f 0.1f cp (to -26v) r bn c off v off (to -20v) 3k ? lx r n1 r n2 20k ? v ref pg_ldon 0.4v q2 figure 22. v off functional block diagram - + - + gml ldo_log pg_ldol 1: n1 fbl drvl v in or v prot (3v to 6v) 20k ? r l2 r l1 c log v logic (1.3v to 3.6v) 0.9v 10f 500 ? r bl q5 figure 23. v logic functional block diagram
el7585a fn7523 rev 3.00 page 13 of 19 march 9, 2006 more output current under the low dropout condition (forced beta of 10). typical v logic voltage supported by el7585a ranges from +1.3v to v dd -0.2v. a fault comparator is also included for monitoring the ou tput voltage. the undervoltage threshold is set at 25% below the 1.2v reference. set-up output voltage refer to the typical application diagram, the output voltages of v on , v off , and v logic are determined by the following equations: where v ref = 1.2v, v refn = 0.2v. resistor networks in the order of 250k ? , 120k ? and 10k ? are recommended for v on , v off and v logic , respectively. charge pump to generate an output voltage higher than v boost , single or multiple stages of charge pumps are needed. the number of stage is determined by the in put and output voltage. for positive charge pump stages: where v ce is the dropout voltage of the pass component of the linear regulator. it range s from 0.3v to 1v depending on the transistor. v f is the forward-voltage of the charge pump rectifier diode. the number of negative charge pump stages is given by: to achieve high efficiency and lo w material cost, the lowest number of charge pump stages which can meet the above requirements, is always preferred. high charge pump output voltage (>36v) applications in the applications where the c harge pump output voltage is over 36v, an external npn transi stor need to be inserted into between drvp pin and base of pass transistor q3 as shown in figure 24; or the linear re gulator can control only one stage charge pump and regu late the final charge pump output as shown in figure 25. discontinuous/continuous boost operation and its effect on the charge pumps the el7585a v on and v off architecture uses lx switching edges to drive diode char ge pumps from which ldo regulators generate the v on and v off supplies. it can be appreciated that should a regular supply of lx switching edges be interrupted, for exam ple during discontinuous operation at light a vdd boost load currents, then this may affect the performance of v on and v off regulation - depending on their exact loading conditions at the time. to optimize v on /v off regulation, the boundary of discontinuous/continuous operat ion of the boost converter can be adjusted, by suitable choice of inductor given v in , v out , switching frequency and the a vdd current loading, to be in continuous operation. v on v ref 1 r 12 r 11 --------- - + ?? ?? ?? ? = --------- - v refn v ref C ?? ? + = --------- - + ?? ?? ?? ? = C + v input 2v f ? C ------------------------------------------------------------- - ? + v input 2v f ? C ------------------------------------------------ - ? v in or a vdd charge pump output 7k ? q3 fbp el7585a drvp npn cascode transistor v on figure 24. cascode npn transistor configuration for high charge pump output voltage (>36v) v on (>36v) 0.1f 0.1f 0.1f 0.1f 7k ? 0.47f 0.22f 0.1f a vdd lx q3 fbp el7585a drvp figure 25. the linear regulator controls one stage of charge pump
el7585a fn7523 rev 3.00 page 14 of 19 march 9, 2006 the following equation gives the boundary between discontinuous and continu ous boost operation. for continuous operati on (lx switching every clock cycle) we require that: i(a vdd _load) > d*(1-d)*v in /(2*l*f osc ) where the duty cycle, d = (a vdd - v in )/a vdd for example, with v in = 5v, f osc = 1.0mhz and a vdd = 12v we find continuous operation of the boost converter can be guaranteed for: l = 10h and i(a vdd ) > 61ma l = 6.8h and i(a vdd ) > 89ma l = 3.3h and i(a vdd ) > 184ma charge pump output capacitors ceramic capacitors with low esr are recommended. with ceramic capacitors, the output ripple voltage is dominated by the capacitance value. the capacitance value can be chosen by the following equation: where f osc is the switching frequency. start-up sequence figure 26 shows a detailed start-up sequence waveform. for a successful power-up, there should be si x peaks at v cdly . when a fault is detected, the device will latch off until eithe r en is toggled or the in put supply is recycled. when the input voltage (v dd ) exceeds 2.5v, v ref and v logic turn on. at the same time, if en is tied to v dd , an internal current sourc e starts to charge c dly to an upper threshold using a fast ramp followed by a slow ramp. if en is low at this point, the c dly ramp will be delayed until en goes high. the first four ramps on c dly (two up, two down) are used to initialize the fault protection switch and to check whether there is a fault condition on c dly or v ref . if a fault is detected, the outputs and the input protection will turn off, but v ref will stay on. if no fault is found, c cdly continues ramping up and down. during the second ramp, the device checks the status of v ref and over temperatur e. at the peak of the second ramp, pg output goes low and enables the input protection pmos q1. q1 is a controlled fet used to prevent in-rush current into v boost before v boost is enabled internally. its rate of turn on is controlled by c o . when a fault is detected, m1 will turn off and disconnect the inductor from v in . with the input protection fe t on, node1 (see typical application diagram) will rise to ~v in . initially the boost is not enabled so v boost rises to v in -v diode through the output diode. hence, there is a step at v boost during this part of the start-up sequence. if this step is not desirable, an external pmos fet can be used to delay the output until the boost is enabled internally. the delayed output appears at a vdd . for el7585a, v boost soft-start at the beginning of the third ramp. the soft-start ramp depends on the value of the c dly capacitor. for c dly of 220nf, the soft-start time is ~2ms. v off turns on at the start of the fourth peak. at the fifth peak, the open drain o/p delb goes low to turn on the external pmos q4 to generate a delayed v boost output. v on is enabled at the beginni ng of the sixth ramp. a vdd , pg, v off , delb and v on are checked at end of this ramp. fault protection during the startup sequence, p rior to boost soft-start, v ref is checked to be within 20% of its final value and the device temperature is check ed. if either of these are not within the expected range, the part is disabled until the power is recycled or en is toggled. if c delay is shorted low, then th e sequence will not start, while if c delay is shorted h, the fir st down ramp will not occur and the sequence will not complete. once the start-up sequence is completed, the chip continuously monitors c dly , delb, fbp, fbl, fbn, v ref , fbb and pg and checks for fa ults. during this time, the voltage on the c dly capacitor remains at 1.15v until either a fault is detected, or t he en pin is pulled low. a fault on c delay , v ref or temperature will shut down the chip immediately. if a fault on any other output is detected, c delay will ramp up linearly with a 5a (typical) current to the upper fault thres hold (typically 2.4v), at which point the chip is disabled unt il the power is recycled or en is toggled. if the fault condition is remov ed prior to the end of the ramp, the voltage on the c dly capacitor ret urns to 1.15v. typical fault thresholds for fbp, fbl, fbn and fbb are included in the tables. pg and delb fault thresholds are typically 0.6v. c int has an internal current-l imited clamp to keep the voltage within its normal range. if c int is shorted low, the boost regulator will attemp t to regulate to 0v. if c int is shorted h, the regulator switches to p mode. if any of the regulated outputs (v boost , v on , v off or v logic ) are driven above their target levels the drive circuitry will switch off until t he output retur ns to its expec ted value. if v boost is excessively loaded, the current limit will prevent damage to the chip. whi le in current limit, the part acts like a current source and th e regulated output will drop. if the output drops be low the fault threshold, a ramp will be initiated on c delay and, provided that the fault is sustained, the chip will be disabled o n completion of the ramp. c out i out 2v ripple f osc ? ? ------------------------------------------------------ ? el7585a
el7585a fn7523 rev 3.00 page 15 of 19 march 9, 2006 in some circumstances, (dependi ng on ambient temperature and thermal design of the boa rd), continuous operation at current limit may result in the over-temperature threshold bein g exceeded, which will cause the part to disable immediately. all i/o also have esd protection, which in many cases will also provide overvoltage protection, relative to either ground or v dd . however, these will not ge nerally operate unless abs max ratings are exceeded. component selection for start-up sequencing and fault protection the c ref capacitor is typically set at 220nf and is required to stabilize the v ref output. the range of c ref is from 22nf to 1f and should not be more than five times the capacitor on c del to ensure correct start-up operation. the c del capacitor is typically 22 0nf and has a usable range from 47nf minimum to several microfarads - only limited by the leakage in the capacitor reaching a levels. c del should be at least 1/5 of the value of c ref (see above). note with 220nf on c del the fault time-out will be typically 50ms and the use of a larger/smal ler value will vary this time proportionally (e.g. 1f will giv e a fault time-out period of typically 230ms). fault sequencing the el7585a has an advanced f ault detection system which protects the ic from both adjacent pin s horts during operation and shorts on the output supplies. a high quality layout/design of the pcb, in respect of grounding quality and dec oupling is necessary to avoid falsely triggering the fault detection sc heme - especially during start - up. the user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and protot ype pcb generation.
el7585a fn7523 rev 3.00 page 16 of 19 march 9, 2006 v cdly en v ref v boost v logic v off delayed v boost v on pg on a vdd soft-start v off on delb on v on soft-start fault detected chip disabled normal operation fault present start-up sequence timed by c dly v ref , v logic on t os t on t del1 figure 26. start-up sequence v in t del3 t del2
el7585a fn7523 rev 3.00 page 17 of 19 march 9, 2006 over-temperature protection an internal temperature sensor continuously monitors the die temperature. in the ev ent that the die temperature exceeds the thermal trip point of 140c , the device will shut down. layout recommendation the device's perform ance including effici ency, output noise, transient response and control loop stability is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. there are some general guidelines for layout: 1. place the external power com ponents (the input capacitors, output capacitors, boost inducto r and output diodes, etc.) in close proximity to the devic e. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v ref and v dd bypass capacitors close to the pins. 3. minimize the length of traces carrying fast signals and high current. 4. all feedback networks should sense the output voltage directly from the point of loa d, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connect ed at only one poi nt near the main decoupling capacitors. 6. the exposed die plate, on the underneath of the package, should be soldered t o an equivalent ar ea of metal on the pcb. this contact area s hould have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb , the amount o f copper track and ground plane area connected to the exposed die plate should be maximized and spre ad out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. a signal ground plane, sepa rate from the power ground plane and connected t o the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (r 1 , r 11 , r 41 ) and the v ref capacitor, c 22 , the c delay capacitor c 7 and the integrator capacitor c 23 . 9. minimize feedback input track lengths to avoid switching noise pick-up. a two-layer demo board is availa ble to illustrate the proper layout implementation. a four-l ayer demo board can be used to further optimize the la yout recommendations. demo board layout figure 27. top layer figure 28. bottom layer
el7585a fn7523 rev 3.00 page 18 of 19 march 9, 2006 typical application diagram note: the sgnd should be connected to the exposed die plate and connected to the pgnd at one point only. lx fbb delb cint drvp fbp drvn fbn pgnd pg cdelay vdd en vref drvl fbl sgnd v in c 10 4.7f node 1 v logic (2.5v) c 31 4.7f c 41 0.1f r 43 500 ? c 22 0.1f r 42 5.4k ? r 41 5k ? r 7 10k ? v ref c 6 4.7f r 6 10 ? c 7 0.22f q 1 c 0 1nf c 1 10f x2 node 1 l 1 6.8h lx d 1 r 2 46.5k ? r 1 5k ? c 2 10f r 9 1m ? c 16 22nf c 9 0.1f r 8 10k ? a vdd (12v) c 23 4.7nf c p 1nf r 13 7k ? q 3 c 14 0.1f c 15 0.47f r 11 20k ? r 12 230k ? r 23 3k ? r 22 104k c 20 4.7f r 21 20k c 25 0.1f d 21 c 12 0.1f d 12 d 11 c 24 0.1f q 2 c 13 0.1f c 11 0.1f v on (15v) v off (-5v) lx lx v ref q 5 q 4 x2 r 7 open c 7 open r 10 10k ?
fn7523 rev 3.00 page 19 of 19 march 9, 2006 el7585a intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. qfn package outline drawing note: the package drawing shown here may not be the latest versi on. to check the latest revision , please refer to the intersil website at http://www.intersil.com/design/packages/index.asp

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